by | Jan 20, 2026

  • R. Kanish, K. S. V. Rohit, Y. Sengupta and M. Rao, “VPSA: A Vectored Processing Element configured Systolic Array Architecture Generator,” 2025 28th Euromicro Conference on Digital System Design (DSD), Salerno, Italy, 2025, pp. 81-87, doi: 10.1109/DSD67783.2025.00023.